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SOC Micro-Architect and RTL Designer

MatX · Mountain View (HQ) or Remote

CHECKED 8H AGO

Infrastructureremote$160k–$600k
Apply on the lab’s site ↗

At a glance

Highlights

  • Build vertically integrated silicon to systems for AGI compute platform.
  • Own subsystems end-to-end from micro-architecture to sign-off-ready design.
  • Create best-in-class silicon for high-performance sustainable GenAI workloads.

What they offer

  • 4 weeks PTO + 12 holidays + up to 3 weeks remote work
  • Company-subsidized medical, dental, vision and life insurance
  • 401K with up to 5% company contribution plus disability coverage
  • $1500 annual professional development budget
  • Onsite lunch and dinner plus paid daily commute

Ideal candidate

End-to-end silicon owner who loves taking subsystems from architecture to tapeout and sweating performance, power and area. You thrive collaborating with verification and physical design to ship sustainable GenAI compute.

Requirements

  • Concept-to-silicon experience driving subsystem or top-level ASIC/SOC design to production
  • 5+ years experience with SystemVerilog, Python, C/C++ for chip design flows
  • Production-proven silicon micro-architecture for high-performance compute or connectivity
  • Experience testing designs with verification teams to close performance and coverage
  • Hands-on synthesis, equivalence checking, lint and CDC to high-quality sign-off
  • Experience with DFT and physical design concepts for test coverage and PPA closure
remote policy
Hybrid, 3 days in office Tuesday through Thursday

Lab profile

About MatX

Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.

What they build

  • AI accelerator silicon for GenAI training and inference
  • Rack-scale AI data center systems
  • Full-stack silicon-to-software platform for large ML workloads

Known for

  • Vertically integrated silicon-to-systems design
  • AI accelerator architecture and performance modeling for LLMs
  • High-efficiency power architecture from chip to rack
  • Silicon verification and software-hardware co-verification
More about MatX →
Apply on the lab’s site ↗