System Software Engineer, Linux Kernel and Device Drivers
MatX · Mountain View
CHECKED 7H AGO
Infrastructureremotesenior
At a glance
Highlights
- Own host software that brings new AI accelerator silicon from prototype to life.
- Debug first silicon side-by-side with hardware and firmware teams on novel chips.
- Feed software lessons back into next-generation AI chip architecture decisions.
What they offer
- 100% paid daily commute via company Uber account or train reimbursement
- $50/mo flexible perk allowance
- $35/mo cell and $40/mo wifi reimbursement
- Up to $1000 home office setup via Amazon business account
- 100% paid mental health benefit via SpringHealth and Guardian EAP
- Up to 12 weeks paid parental leave plus 10 weeks pregnancy disability leave
Ideal candidate
Self-driven systems builder with 8+ years bringing chips to life who loves owning hardware-adjacent software from blank page to bring-up and thrives debugging ambiguous cross-stack problems with minimal hand-holding.
Requirements
- BS or higher in Computer Science, Electrical Engineering or equivalent with 8+ years in low-level systems software
- Strong hands-on Linux kernel development with shipped device drivers, ideally for PCIe devices
- Strong C programming in userspace and kernel space
- Able to program a device from hardware datasheets and register definitions
- Deep understanding of computer architecture and OS internals including MMIO, DMA, interrupts, IOMMU and virtual memory
- Experienced debugging complex hardware/software interaction with limited visibility
- Self-driven and comfortable owning components from blank page through bring-up on a small team
Lab profile
About MatX
Designs vertically integrated AI silicon and systems to run frontier models at physics-limit efficiency.
What they build
- AI accelerator silicon for GenAI training and inference
- Rack-scale AI data center systems
- Full-stack silicon-to-software platform for large ML workloads
Known for
- Vertically integrated silicon-to-systems design
- AI accelerator architecture and performance modeling for LLMs
- High-efficiency power architecture from chip to rack
- Silicon verification and software-hardware co-verification