Advanced Packaging Reliability Engineer

Highlights

• Lead package reliability for AI-native silicon powering frontier models.
• Optimize large HPC packages via thermo-mechanical modeling and simulation.
• Drive qualification from architecture through high-volume manufacturing.

What they offer

• Equity

Ideal candidate

A seasoned hardware reliability leader who loves solving complex HPC packaging challenges and pushing heterogeneous integration limits through simulation-driven design and cross-functional collaboration.

Requirements

• 8+ years of industry experience & knowledge of semiconductor package reliability principles and failure mechanisms, including electromigration, solder-joint fatigue, interfacial delamination, dielectric cracking, via failure, warpage, creep, stress relaxation, and material degradation.
• In-depth knowledge of advanced packaging architectures, including 2.5D and 3.5D integration, interposers, embedded bridges, chiplets, large package substrates, HBM integration, redistribution layers, and package-level power delivery.
• Demonstrated experience leading package failure investigations, performing root-cause analysis, and implementing effective design, material, process, or manufacturing corrective actions.
• Strong experience with thermal and mechanical finite-element modeling of packages, including temperature distribution, warpage, stress, strain, fatigue, and interfacial reliability.
• Strong understanding of package-material behavior, including coefficient of thermal expansion, elasticity, viscoelasticity, plasticity, creep, adhesion, fracture toughness, thermal conductivity, and temperature-dependent properties.