ASIC Package SI/PI Engineer

Highlights

• Own SI/PI architecture for advanced AI ASIC packages from feasibility to production.
• Co-design chips, systems and packages powering next-gen frontier models.
• Optimize power-delivery networks and 2.5D/3D package electromagnetics.

What they offer

• Equity

Ideal candidate

Hands-on hardware engineer who loves turning simulations into real package designs and thrives collaborating across ASIC, package and system teams to ship frontier AI silicon.

Requirements

• 5+ years of experience in signal integrity, power integrity, high-speed interconnect design, PDN design and package electrical design
• Strong understanding of signal-integrity and power-integrity fundamentals, including transmission-line behavior, impedance, loss, crosstalk, return paths, power-distribution networks, inductance, decoupling, voltage droop, and current distribution
• Hands-on experience with electromagnetic and SI/PI simulation tools such as Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI/PowerDC, or equivalent
• Experience with package layout environments such as Cadence APD/SIP, including the ability to review and modify package structures for SI/PI optimization
• Experience developing automated design optimization flows for model extraction, simulation setup, post-processing, design-space exploration, or layout optimization
• Strong communication skills and the ability to work effectively across ASIC, package, PCB, system, mechanical, thermal, power, validation, and manufacturing teams