RTL Design Engineer – Interconnect & Network Datapath

Highlights

• Own on- and off-chip communication for a custom AI accelerator platform.
• Drive scalable fabrics connecting high-bandwidth compute, memory and I/O.
• Co-design chips and systems powering the next generation of frontier models.

What they offer

• equity

Ideal candidate

Hands-on senior silicon owner who thrives on end-to-end delivery from architecture to production silicon. You balance performance, pragmatism and mentorship while sweating quality at scale.

Requirements

• Extensive experience with recent hands-on ownership of networking or packet-switched interconnect RTL
• Expertise in Verilog/SystemVerilog for clean, parameterized production-quality RTL
• Track record owning major RTL blocks from microarchitecture through tape-out and bring-up
• Experience with routing, arbitration, flow control, QoS, ordering and deadlock avoidance
• Familiarity with AXI, CHI, CXL, PCIe or Ethernet alongside packet-datapath expertise
• Familiarity with lint, CDC/RDC, synthesis, formal, STA, power and DFT flows
• Ability to mentor engineers and collaborate across architecture, verification and physical design