RTL Design Engineer, Networking / NoC

Highlights

• Design next-generation AI accelerator silicon for frontier models.
• Co-design chips, systems and tools for OpenAI supercomputing platform.
• Influence architecture decisions across hardware and software co-design.

What they offer

• Equity

Ideal candidate

Hands-on silicon designer who loves ambiguous, high-performance challenges and owning designs end-to-end. You thrive co-designing hardware with software and architecture partners to power frontier AI workloads.

Requirements

• Strong hands-on ASIC RTL design and microarchitecture development using SystemVerilog or Verilog
• Experience designing complex digital blocks from specification through RTL development and verification
• Understanding of performance, power, area, latency and throughput tradeoffs
• Experience collaborating with architecture, software, verification and physical design teams
• Experience with synthesis, timing closure and physical implementation considerations
• Experience with NoC, networking, interconnect fabrics or high-bandwidth data movement