Design Verification Engineer, New Grad
SambaNova · San Jose, California, United States · Austin, TX · San Jose, CA
Infrastructureonsiteentry-level$120k–$150k
At a glance
Highlights
- Verify the RDU AI chip powering rack-scale inference for agentic workloads.
- Build verification for chip control, sequencing, clocking and recovery flows.
- Debug regressions with designers to find bugs before tape-out.
What they offer
- Equity
- 95% employee medical premium coverage, 77% for dependents
- HSA with employer contribution, dental and vision
- Disability, life and AD&D insurance plus FSAs
- Headspace, Gympass+, One Medical and EAP well-being benefits
Ideal candidate
New EE/CE/CS grad energized by chip bring-up and debugging who enjoys digging into complex control logic and collaborating closely with designers to chase corner cases to closure.
Requirements
- B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Coursework or project experience in digital design and computer architecture
- Experience with SystemVerilog or Verilog
- Scripting experience in Python, Perl, TCL, or shell
- Experience with UVM
- Familiarity with constrained-random verification, functional coverage, and assertions
- Familiarity with clock domain crossing concepts
Lab profile
About SambaNova
Full-stack AI infrastructure with RDU dataflow chips for fast agentic inference.
What they build
- RDU Reconfigurable Dataflow Unit
- SambaRack rack-scale hardware
- Full-stack AI inference platform
Known for
- Reconfigurable dataflow architecture alternative to GPUs
- High decode performance for agentic workloads
- Full-stack hardware-software co-design
Key facts
- Founded in 2017
- Headquartered in Palo Alto, California
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