Director of ASIC Design Verification

Highlights

• Own end-to-end verification for next-generation RDU AI chips to tape-out.
• Verify dataflow architecture delivering strong decode for agentic workloads.
• Carry ownership into lab for first-silicon validation and bring-up debug.

What they offer

• Equity
• 95% employee medical premium coverage
• 77% dependent medical premium coverage
• HSA with employer contribution
• Dental and vision insurance
• Short/long-term disability insurance
• Basic life, voluntary life and AD&D insurance
• FSA options including Health Care, Limited Purpose and Dependent Care
• Headspace subscription
• Gympass+ membership with access to physical gyms
• One Medical membership
• Employee Assistance Program counseling services

Ideal candidate

Deep verification leader combining hands-on technical authority with team leadership. You hold strong methodology opinions, thrive on the hardest debug, and enjoy coaching principal engineers to deliver quality silicon on schedule.

Requirements

• Own pre-silicon functional and performance verification for ASICs through tape-out
• Define verification architecture, strategy, schedules and DV environments for complex ML ASICs
• Serve as technical authority on testbench architecture, coverage and sign-off criteria
• Lead debug on hardest failures and own tape-out readiness sign-off
• Support lab functional validation and bring-up debug for first silicon
• Lead, coach and retain team of 8-10 engineers including principal-level engineers
• Deep understanding of performance verification methodology
• High-performance interconnect protocols (PCIe, Ethernet) and memory subsystems
• Advanced TSMC nodes and multi-die or chiplet verification challenges
• Emulation and FPGA prototyping platforms
• Managing cross-site or distributed teams
• Fluency with Claude or other AI tools applied to verification