Principal Design Verification Engineer

Highlights

• Own end-to-end verification for a major subsystem of next-gen RDU silicon.
• Verify the chip against production ML workloads with principal engineers.
• Contribute to emulation, FPGA prototypes and post-silicon debug in the lab.

What they offer

• Equity
• 95% employee medical premium coverage, 77% for dependents
• HSA with employer contribution
• Dental, Vision and disability / life / AD&D insurance
• FSA options including Health Care and Dependent Care
• Headspace subscription and Gympass+ membership
• One Medical membership and Employee Assistance Program

Ideal candidate

Senior verification owner who thrives on hard debug and coverage closure, leads through technical influence, and cares about building reusable methodology and mentoring others on complex silicon.

Requirements

• BS or MS in EE, CS, or CE with 7+ years of industry experience in ASIC design verification
• Deep hands-on expertise in SystemVerilog and SVA with UVM, OVM, or VMM, plus Python and C/C++ scripting
• Full-cycle DV ownership from test plan through tape-out including owning a coverage model to closure
• Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC
• Track record debugging hard, intermittent or low-reproducibility pre-silicon failures to root cause
• Demonstrated technical leadership without formal authority, including mentoring engineers
• Working knowledge of modern computer architecture and ML accelerators or SoCs