Principal Design Verifiction Engineer

Highlights

• Own verification for major subsystem of next-gen RDU AI chip.
• Verify dataflow silicon against real ML and agentic workloads.
• Shape verification methodology and reusable infrastructure team-wide.

What they offer

• Equity
• 95% premium coverage for employee medical insurance and 77% for dependents
• Health Savings Account (HSA) with employer contribution
• Dental and vision insurance
• Short/long-term disability, basic life, voluntary life and AD&D insurance
• Flexible Spending Account options
• Headspace subscription
• Gympass+ membership with access to physical gyms
• One Medical membership
• Employee Assistance Program counseling services

Ideal candidate

Senior verification owner who thrives on hard debug and end-to-end ownership of complex silicon. You set technical direction, mentor others, and care about verifying real AI workloads.

Requirements

• BS or MS in EE, CS, or CE with 7+ years of industry experience in ASIC design verification
• Deep hands-on expertise in SystemVerilog and SVA with UVM, OVM or VMM, plus Python and C/C++ scripting
• Full-cycle DV ownership from test plan through tape-out on a complex ASIC or major subsystem including coverage closure
• Experience verifying digital logic in a CPU, GPU, SoC or comparably complex ASIC
• Track record debugging hard, intermittent or low-reproducibility pre-silicon failures to root cause
• Demonstrated technical leadership without formal authority, including reviews and mentoring engineers
• Working knowledge of modern computer architecture and ML accelerators or SoCs