Principal RTL Design Engineer

Highlights

• Own microarchitecture and RTL for next-gen RDU AI accelerator.
• Take major compute, memory and network blocks from spec to tape-out.
• Build dataflow silicon for agentic AI, codegen and long-run apps.

What they offer

• Equity
• 95% employee medical coverage, 77% for dependents
• HSA with employer contribution
• Dental and vision coverage
• Short/long-term disability and life insurance
• FSA options
• Headspace subscription
• Gympass+ membership
• One Medical membership
• Employee Assistance Program

Ideal candidate

Seasoned ASIC owner who loves pushing frequency and PPA limits and guiding design decisions. You mentor others and sweat the details from spec through tape-out.

Requirements

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science
• 7+ years of industry experience in ASIC RTL design
• Mastery of synthesizable SystemVerilog including SVA
• High-frequency design with datapath pipelining and retiming
• Strong foundation in computer architecture and digital logic design
• Ownership of complex block from spec through tape-out
• Experience converging power, performance and area with physical constraints
• Hands-on synthesis, STA, lint, CDC and LEC flows
• Technical leadership and mentoring without formal authority
• Scripting in Python for design and flow automation