Principal RTL Design Engineer, IO & Memory Systems

Highlights

• Own high-speed IO and memory subsystems for the DataScale AI platform.
• Build RDU-based rack-scale hardware for faster, energy-efficient AI inference.
• Drive subsystems from architecture exploration through to silicon delivery.

What they offer

• Equity
• 95% employee medical premium coverage, 77% for dependents
• Health Savings Account with employer contribution
• Dental, vision and FSA options
• Short/long-term disability, life and AD&D insurance
• Headspace subscription and Gympass+ membership
• One Medical membership and Employee Assistance Program

Ideal candidate

A hands-on owner with deep ASIC design experience who thrives in ambiguity and loves taking complex subsystems from concept to silicon. Collaborative and proactive, you care about performance, efficiency, and reliable AI systems at scale.

Requirements

• MS in Electrical Engineering, Computer Science, or related field
• 7+ years of experience in ASIC design
• Experience in logic design, microarchitecture, specification, SystemVerilog RTL and verification
• Experience with power, performance or area optimization
• Experience with two or more protocols such as AXI, APB, PCIe, Ethernet or UCIe
• Experience with memory subsystems such as HBM and CXL
• Ability to evaluate vendor IP and distill complex specs into design requirements
• Clear, proactive and collaborative communicator