Senior RTL Design Engineer

Highlights

• Own RTL blocks for the RDU AI accelerator from microarchitecture through tape-out.
• Carry designs through implementation, tape-out, and silicon bring-up.
• Help advance rack-scale AI inference built on dataflow architecture, not GPUs.

What they offer

• Equity
• Medical insurance with 95% employee and 77% dependent premium coverage
• Health Savings Account with employer contribution
• Dental and vision coverage
• Short-term and long-term disability insurance
• Basic life, voluntary life and AD&D insurance
• Flexible Spending Accounts
• Headspace subscription
• Gympass+ membership
• One Medical membership
• Employee Assistance Program counseling

Ideal candidate

An experienced ASIC designer who loves owning blocks end-to-end, from architecture to silicon, and cares deeply about performance, efficiency, and building next-gen AI accelerators.

Requirements

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science
• 5+ years of experience in ASIC RTL design
• Solid foundation in computer architecture and digital logic design
• Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
• Experience making design decisions that trade off power, performance, and area
• Knowledge of interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
• Experience with digital logic synthesis tools and static timing analysis
• Proficiency with tools for linting, clock domain crossing, and logical equivalence checking
• Experience implementing SystemVerilog Assertions to check design intent
• Familiarity with tools and simulators for hardware performance analysis and tuning
• Familiarity with Git for managing release cycles
• Scripting skills in Python and Linux shell