Senior/Lead VLS Engineer - Global Circuits

Highlights

• Architect ultra-low-jitter clock networks for next-gen AI inference chips.
• Own chip-level PLL, IO, ESD and latch-up strategy and integration.
• Help scale RDU-powered racks from prototype to mass production.

What they offer

• Equity plus competitive total rewards package
• 95% employee medical premium coverage, 77% for dependents
• HSA with employer contribution, dental, vision and FSA options
• Short/long-term disability, basic, voluntary life and AD&D insurance
• Headspace, Gympass+, One Medical membership and EAP

Ideal candidate

Seasoned custom analog/mixed-signal designer who thrives owning chip-level clocking and reliability from architecture to silicon bring-up and cares about precision, low power, and robust high-performance AI hardware.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or Microelectronics
• 8+ years of custom analog/mixed-signal VLSI design experience in advanced nodes including 7nm, 5nm, 3nm, 2nm
• Experience designing custom clock networks, low-power design techniques, and custom IO/ESD/Latch-Up circuits
• Deep knowledge of physical layout for high-speed clocking, parasitic extraction and low-resistance interconnects
• 10+ years of industry experience with track record driving complex top-level silicon integrations
• Experience leveraging AI tools and scripting in Python, TCL, SKILL for flow automation and simulation post-processing