Performance Engineer, Kernels

Highlights

• Own the kernel layer behind multi-tenant serving across a large GPU fleet.
• Serve small and large LLMs, MoE, streaming Indic ASR, and multimodal models.
• Ship code that directly moves production p99 latency and serving cost.

Ideal candidate

A systems-obsessed performance engineer with real kernel-shipping depth who has beaten baselines in production. You sweat microsecond details and care about owning p99 and cost at fleet scale.

Requirements

• 5+ years in ML systems with 2+ years authoring production CUDA kernels
• Shipped production kernel beating prior baseline by measurable margin
• CUDA kernel-authoring expertise including thread-block sizing, shared memory, warp primitives, async copies and MMA selection
• CUTLASS / CuTe DSL modify-and-extend ability with layout algebra comfort
• PTX debug-and-modify ability including hand-written PTX
• Nsight Compute and Nsight Systems fluency with roofline analysis
• Authored or modified at least one attention kernel (FlashAttention-family, paged, MLA, sliding-window, or sparse)
• Multi-architecture awareness of Hopper to Blackwell changes including TMA, WGMMA and tcgen05