CPU Microarchitect, Vector and Matrix Compute
Tenstorrent · Santa Clara, California, United States; Spain · North America
CHECKED 22H AGO
Infrastructureonsite$100k–$500k
At a glance
Highlights
- Drive architecture of RISC-V vector, floating-point and matrix execution units.
- Shape next-gen CPU compute for HPC and AI inference and training workloads.
- Define scalable compute architectures optimizing performance, power and area.
What they offer
- Base and variable compensation targets
- Highly competitive compensation package and benefits
Ideal candidate
Passionate architect who loves working across hardware and software to shape next-gen AI and HPC compute. Collaborative, curious problem-solver excited by performance, scalability and open RISC-V innovation.
Requirements
- 5+ years of experience in CPU design for high-performance computing and AI acceleration
- Experience designing hardware for matrix floating-point computation, AI accelerators, vector processing, tensor engines, or machine learning workloads
- Knowledge of CPU architecture, memory hierarchy, data movement, cache coherency, and interactions between CPUs and AI accelerators
- Experience defining architectural specifications and leading cross-functional teams from concept through silicon implementation
- Experience with RTL development with cutting edge AI frontier models
- remote policy
- Remote based out of North America or Spain
- hiring process
- Candidates will be assessed for the appropriate level during the interview process, with offers aligned to that level.
Lab profile
About Tenstorrent
Builds high-performance RISC-V CPUs and AI accelerators with full-stack software for efficient AI computing.
What they build
- AI accelerators
- RISC-V CPUs
- AI software and compilers
Known for
- Custom RISC-V CPU development from scratch
- Full-stack AI hardware and software
- Performance, ease of use and cost efficiency
Key facts
- Founded in 2016
- Headquartered in Toronto, Canada
- Backed by Samsung and Hyundai Motor Group