Front End Design Verification Engineer

Highlights

• Verify the fetch unit for next-gen high-performance out-of-order RISC-V CPUs.
• Tackle speculative execution, branches, redirects and pipeline flush corner cases.
• Drive performance and correctness for CPUs built for demanding AI workloads.

What they offer

• Highly competitive compensation package and benefits

Ideal candidate

A curious, hands-on verification engineer who loves digging into complex processor behavior and hunting subtle bugs. You thrive collaborating with architects and designers and care about real-world CPU performance.

Requirements

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development
• Solid understanding of CPU architecture including pipelines, instruction fetch/decode, branch prediction, speculative or out-of-order execution
• Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools
• Strong programming skills in C/C++ and/or Python with ability to collaborate across architecture, RTL, DV, and software teams