Interconnect and Compute Architect

Highlights

• Define next-generation CPU networking architecture for datacenter and robotics.
• Seed and specify future low-power devices for AI/ML compute and sensor ingest.
• Build extreme low-latency networks for high-performance AI workloads.

What they offer

• Highly competitive compensation package and benefits
• Base and variable compensation targets

Ideal candidate

You thrive in ambiguity, juggling multiple priorities while collaborating across hardware, software and systems. Curious and driven, you care about pushing AI performance and solving hard architecture problems.

Requirements

• Knowledge of Ethernet network architecture and how performance is modeled
• Experience with die-to-die interfaces, protocols and design tradeoffs
• Understanding of Ethernet networking concepts mapped to on-chip and off-chip fabrics
• Experience with datacenter scale-up architectures like UALink, NVLink and Broadcom SUE
• Experience with scale-out RDMA protocols like RoCE and InfiniBand
• Comfortable at intersection of forwarding, buffering, modeling and RTL design
• Ability to collaborate across hardware, software and systems teams