Physical Design CPU Methodology Engineer
Tenstorrent · Santa Clara, California, United States · United States
CHECKED 22H AGO
Infrastructureonsite$100k–$500k
At a glance
Highlights
- Define RTL-to-GDS methodology for high-performance CPU cores.
- Explore AI/ML-enabled physical design for prediction and flow tuning.
- Scale CPU methodology and automation across advanced-node programs.
What they offer
- Highly competitive compensation package
- Benefits
Ideal candidate
Experienced physical design leader passionate about high-performance CPUs and scalable methodology. Collaborative mentor who thrives driving standards across distributed teams and applying AI to hard implementation challenges.
Requirements
- 10+ years of ASIC/SoC/CPU experience, ideally focused on high-performance CPUs
- Deep expertise across RTL-to-GDS implementation and signoff including timing closure, power, SI, EM/IR, extraction and physical verification
- Experience building or owning physical design methodology, automation or CAD flows
- Highly skilled in Tcl, Python, Perl or similar scripting languages
- Technical leadership ability to influence across teams and mentor engineers across distributed organizations
- remote policy
- Remote based in United States
- hiring process
- Candidates will be assessed for the appropriate level during the interview process, with offers aligned to that level.
Lab profile
About Tenstorrent
Builds high-performance RISC-V CPUs and AI accelerators with full-stack software for efficient AI computing.
What they build
- AI accelerators
- RISC-V CPUs
- AI software and compilers
Known for
- Custom RISC-V CPU development from scratch
- Full-stack AI hardware and software
- Performance, ease of use and cost efficiency
Key facts
- Founded in 2016
- Headquartered in Toronto, Canada
- Backed by Samsung and Hyundai Motor Group