Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Highlights

• Drive die-to-die physical implementation from RTL to GDSII for AI hardware.
• Close high-speed die-to-die interfaces for multi-die chiplet architectures.
• Take high-speed D2D PHYs and controllers from netlist to tapeout.

What they offer

• Base and variable compensation targets
• Highly competitive compensation package and benefits

Ideal candidate

A seasoned, detail-oriented problem solver who thrives on hard closure challenges and collaborating across analog, digital and full-chip teams to deliver high-speed multi-die designs.

Requirements

• 5+ years ASIC physical design experience at advanced nodes (7nm or below) with multiple successful tapeouts
• Own blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS and sign-off
• Experience closing high-speed interfaces such as D2D, PCIe, HBM and SerDes including timing, signal and power integrity
• Proficient in STA, constraints and closure for complex high-speed designs
• Experience with EDA tools from Synopsys, Cadence and Mentor for implementation and verification
• Experience with Tcl and Python for flow automation and methodology improvements
• B.S./M.S. in EE, CE or related field