Physical Design Engineer - STA
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Austin · Fort Collins · Santa Clara
CHECKED 23H AGO
Infrastructureonsite$100k–$500k
At a glance
Highlights
- Drive timing closure for complex, high-performance chip designs.
- Close timing on high-performance RISC-V CPUs and AI SoCs.
- Collaborate across logic, DFT and physical design to hit performance targets.
Ideal candidate
An experienced, analytical and detail-oriented timing engineer who loves chasing aggressive performance goals. Collaborative across teams, resourceful and self-driven, with a passion for AI hardware and solving hard problems.
Requirements
- 7+ years of industry experience and a proven record of successful tapeouts.
- Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
- Proficiency in writing and debugging SDC constraints, creating ECOs, and developing closure strategies.
- Strong scripting skills in Python, Perl, and TCL to support automation and flow development.
- Familiarity with SPICE modeling and worst-case corner analysis.
- remote policy
- hybrid
- hiring process
- Candidates will be assessed for the appropriate level during the interview process, and offers will align with that level.
Lab profile
About Tenstorrent
Builds high-performance RISC-V CPUs and AI accelerators with full-stack software for efficient AI computing.
What they build
- AI accelerators
- RISC-V CPUs
- AI software and compilers
Known for
- Custom RISC-V CPU development from scratch
- Full-stack AI hardware and software
- Performance, ease of use and cost efficiency
Key facts
- Founded in 2016
- Headquartered in Toronto, Canada
- Backed by Samsung and Hyundai Motor Group