Physical Design Engineer, Timing
Tenstorrent · Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States · Austin · Fort Collins · Santa Clara
CHECKED 23H AGO
Infrastructureonsitemid-senior$100k–$500k
At a glance
Highlights
- Converge multi-million-gate AI designs on advanced process nodes to tapeout.
- Drive timing convergence across blocks, partitions and top-level designs.
- Partner cross-functionally to deliver high-performance RISC-V AI platform.
What they offer
- Highly competitive compensation package and benefits
Ideal candidate
A collaborative physical design engineer who loves solving hard timing and convergence challenges and driving complex AI chips to tapeout across distributed teams.
Requirements
- 8+ years of experience in STA, timing closure, and advanced-node design implementation
- Experience with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding and final signoff
- Skilled in writing and debugging SDC constraints, creating ECOs and analyzing worst-case corners
- Experience with Python, Perl and Tcl for automation and flow development
- Strong collaborator able to drive results across distributed, cross-functional teams
- Must be eligible to access U.S. export-controlled technology
- remote policy
- hybrid
- hiring process
- Candidates will be assessed for the appropriate level during the interview process, with offers aligned to that level.
Lab profile
About Tenstorrent
Builds high-performance RISC-V CPUs and AI accelerators with full-stack software for efficient AI computing.
What they build
- AI accelerators
- RISC-V CPUs
- AI software and compilers
Known for
- Custom RISC-V CPU development from scratch
- Full-stack AI hardware and software
- Performance, ease of use and cost efficiency
Key facts
- Founded in 2016
- Headquartered in Toronto, Canada
- Backed by Samsung and Hyundai Motor Group