Senior DFT Engineer, Architecture

Highlights

• Design and integrate multiple chiplets into a System-in-Package project
• Build chip-level DFT strategies for high-speed CPU core designs
• Collaborate with worldwide experts across the USA, Japan and beyond

Ideal candidate

A collaborative DFT veteran who thrives in complex, high-profile chiplet programs and cares about testability, silicon debug, and delivering robust AI hardware on schedule.

Requirements

• Bachelor, Master or PhD in electrical, computer engineering or computer science
• At least 10 years of relevant industry experience
• Experience with DFT standard tools (e.g. Synopsys/Siemens) is required
• Experience with scripting languages (e.g. TCL, Python) is required
• Experience with DFT planning and SoC silicon debug
• Skills at developing a DFT plan, monitoring indicators and scoping risk to deliver on schedule
• Excellent verbal and written communication in English and collaboration skills